1. Field of the Invention
The present invention relates to a video reproduction system of a video cassette recorder, and more particularly, to a jitter correcting apparatus and method for correcting video signal jitter occurring in a video reproduction system.
2. Description of the Related Art
Generally, video signals displayed on television conform with broadcasting standards. However, the running structure of a tape drive is commonly unstable in a video reproduction system such as a video cassette recorder (VCR), such that jitter can occur in a reproduced video signal. If the reproduced video signal jitters, the horizontal frequency of the video signal changes and thus, the resulting picture on a video screen flickers. As a result, it is difficult to detect an accurate chrominance sub-carrier frequency from a video signal. Accordingly, it is difficult to reproduce colors of the originally recorded signal.
FIG. 1 is a block diagram for explaining a video reproduction system of a conventional VCR. The video reproduction system includes a head 11, an analog signal processor 12, an analog-to-digital converter (ADC) 14, a video decoder 16, a jitter correcting apparatus 18 and a video encoder 20.
The analog signal processor 12 frequency-demodulates a magnetic signal read by the head 11 and outputs an analog video signal which is modulated into a chrominance sub-carrier. The ADC 14 converts the analog video signal output from the analog signal processor 12 into a digital signal. The digitized video signal is decoded by the video decoder 16. The jitter of the decoded video signal Y/U/V is corrected by the jitter correcting apparatus 18 and then output as a video signal Y1/U1/V1 absent jitter. The jitter-free video signal Y1/U1/V1 is encoded by the video encoder 20 and output through an output terminal OUT.
The top and bottom waveforms of FIG. 2A demonstrate synchronizing signals of a video signal-when jitter does not occur and when jitter occurs, respectively. The top and bottom waveforms of FIG. 2B demonstrate pilot signals of a low-band-converted chrominance signal when jitter does not occur and when jitter occurs, respectively.
As shown in FIG. 2A, the horizontal frequency of a jittered video signal shown in the lower portion does not comport with that of a normal jitter-free video signal shown in the upper portion. Similarly, in FIG. 2B, the frequency of the pilot signal of a jittered chrominance signal shown in the lower portion does not comport with that of pilot signal of a normal jitter-free chrominance signal shown in the upper portion.
In a conventional approach for solving these problems, the running structure of a video tape reproduction system is strictly controlled to adjust reproduction speed, thereby improving the jitter and the color reproduction of an image. However, control over the running structure has a mechanical limit, such that correction beyond a certain performance limit cannot be accomplished. In a more advanced method for addressing this issue, a digital signal processing technique is employed to correct video signal jitter.
FIG. 3 is a block diagram for explaining a video signal jitter correcting apparatus using a conventional digital signal processing technique. Referring to FIG. 3, a digital video signal is applied to a digital video demodulator 30 via an input terminal IN and demodulated in response to a write clock signal WCK generated by a phase-locked loop (PLL) 32. The demodulated signal is stored in a memory device 34 in response to the write clock signal WCK. The stored video signal is read in response to a read clock signal RCK having a fixed frequency and applied to a digital video modulator 36. A synchronizing signal separator 37 detects a horizontal synchronizing signal from the input video signal. The detected horizontal synchronizing signal is locked every line in a PLL 32 and thus, a locked write clock signal. WCK is generated. If an input video signal includes jitter, then the write clock signal WCK generated by the PLL 32 also has jitter. In addition, any jitter generated in the PLL 32 may cause jitter of the write clock signal WCK. A video signal which is demodulated by a jittered write clock signal WCK naturally includes jitter. In removing such jitter, the memory device 34 such as a frame or field memory is required. Accordingly, the overall circuit size of a jitter correcting apparatus for a video signal using the conventional digital scheme increases due to the capacity of the memory device 34, and accordingly, the cost of system implementation increases.
Moreover, during sampling operation of the digital video demodulator 30 of FIG. 3, if a write clock signal WCK includes jitter, faithful color reproduction is difficult when demodulating a modulated chrominance signal. The modulated chrominance signal is a signal obtained by modulating a chrominance signal by a carrier frequency. Since the standard of the carrier frequency is established in the unit of several hundreds of parts per million (ppm), the modulated chrominance signal is a very precise signal. On the other hand, the range of jitter appearing in the write clock signal WCK due to jitter in the synchronizing signal or the PLL 32 is very large. Accordingly, when sampling a modulated chrominance signal using a write clock signal WCK, the sampling point also varies according to the jitter. Thus, the sampling value is inaccurate and, as a result, it is difficult to faithfully demodulate the chrominance signal.
In yet another method for correcting jitter in an image, interpolation is used to improve color reproduction without using a frame or field memory. In other words, in the method using interpolation, a jitter-free clock signal is generated by sampling the video signal to demodulate the video signal, and interpolation is used for the output signal. In an analog video signal image, the length of each horizontal line can be varied and thus, the number of pixels of a video signal can be varied according to the length of a horizontal line. However, after the interpolation, the number of pixels becomes constant regardless of the length of a line. In this case, the interpolation has the effect of low pass filtering, and thus the high frequency component of a luminance signal may be blocked. Accordingly, the conventional method of correcting jitter in a video signal using interpolation may cause severe deterioration of the resolution of a luminance signal. Particularly, the jitter correcting method using interpolation is not suitable for a video signal which does not comport with the standard.
To solve the above problems, it is an object of the present invention to provide a jitter correcting apparatus for a video signal, for faithfully reproducing a chrominance signal without deteriorating the resolution of a luminance signal, even though the jitter correcting apparatus uses a memory device with small capacity.
It is another object of the present invention to provide a jitter correction method for a video signal, which is performed by the jitter correcting apparatus.
Accordingly, to achieve the first object in one aspect, there is provided a jitter correcting apparatus for correcting jitter of a video signal in a video signal reproduction system including a digital video decoder for demodulating the externally-applied video signal and a first clock circuit (for example a phase-locked loop) for generating a first clock signal synchronized with the video signal. The jitter correcting apparatus includes an address generator, a comparator and a dual port memory device. The address generator generates a write address for writing the video signal in response to the first clock signal, generates a read address for reading the video signal in response to a second clock signal having a fixed frequency, and corrects the write and read addresses in response to first and second comparison signals. The comparator compares the write address with the read address and generates the first comparison signal and the second comparison signal according to a result of the comparison. The dual port memory device stores the video signal at a location corresponding to the write address in response to the first clock signal and outputs a video signal stored at a location corresponding to the read address in response to the second clock signal.
To achieve the first object in another aspect, there is provided a jitter correcting apparatus for correcting jitter of an externally-applied input video signal in a video signal reproduction system including a digital video decoder for demodulating a luminance signal of the video signal in response to a first clock signal having a variable frequency and demodulating a chrominance signal of the video signal in response to a second clock signal of a fixed frequency. The jitter correcting apparatus includes a luminance signal address generator, a first dual port memory device, a chrominance signal address generator and a second dual port memory device. The luminance signal address generator generates a luminance signal write address for writing the luminance signal in response to the first clock signal, generates a luminance signal read address for reading the luminance signal in response to the second clock signal, compares the luminance signal write address with the luminance signal read address, and corrects the luminance signal read and write addresses based on a result of the comparison. The first dual port memory device stores the luminance signal at a location corresponding to the luminance signal write address in response to the first clock signal and outputs the luminance signal stored at a location corresponding to the luminance signal read address in response to the second clock signal. The chrominance signal address generator generates a chrominance signal write address for writing the chrominance signal and a chrominance signal read address for reading the chrominance signal, in response to the second clock signal, compares the chrominance signal write address with the chrominance signal read address, and corrects the chrominance signal read and write addresses based on a result of the comparison. The second dual port memory device stores the chrominance signal at a location corresponding to the chrominance signal write address and outputs the chrominance signal stored at a location corresponding to the chrominance signal read address, in response to the second clock signal.
To achieve the second object in one aspect, there is provided a jitter correcting method for a video signal, and the method includes steps (a) through (d). In step (a), a write address for the video signal is generated in response to a first clock signal having a variable frequency, and a read address is generated in response to a second clock signal having a fixed frequency. In the step (b), the read address is reset, and then accumulated errors between write addresses and read addresses are corrected at the time when a head switching signal is generated. In the step (c), the approach state between a current write address and a current read address is determined after the step (b), and the write address or the read address is corrected. In the step (d), the video signal is written and read in response to the corrected write address and the corrected read address.
To achieve the second object in another aspect, there is provided a method for correcting jitter of a video signal while writing the video signal composed of a chrominance signal, a luminance signal and horizontal and vertical synchronizing signals into corresponding dual port memory devices and reading the written video signal, and the method includes steps (a) through (e). In the step (a), luminance and chrominance signal write addresses are generated in response to a first clock signal having a variable frequency or in response to a second clock signal having a fixed frequency, and luminance and chrominance signal read addresses are generated in response to the second clock signal. In the step (b), a horizontal cycle of the video signal is corrected, and an error value corresponding to the average skew of a field of the video signal is generated. In the step (c), the luminance and chrominance signal read addresses are reset when a head switching signal is generated in response to the error value, so as to compensate for accumulated errors between write addresses and read addresses. In the step (d), approach states between the luminance and chrominance signal write addresses and the luminance and chrominance signal read addresses, respectively, are determined after the step (c), and the write addresses or the read addresses are corrected. In the step (e), the video signal is written and read in response to the corrected luminance and chrominance signal write and read addresses.